RLV12 Emulator V2.0 Main PCB
Here you can download an archive with the Eagle schematic and the board Main PCB Eagle Files and you can download the following archive with the necessary Gerber and Drill files I used to order the PCB’s Main PCB Gerber Files.
RLV12 Emulator V2.0 Break-Out Board
Here you can download the Break-Out Board Eagle Files and the production files Break-Out Board Gerber Files I plan also to publish a Fusion 360 file for the filler panel that matches the break-out board for a rear I/O distribution panel slot of a BA23 enclosure. I do not own a B23 enclosure but the documentation of my SMS-30 PDP-11 states that the slots provided in the case are the same as in a BA23 enclosure. So for the time being you would have to come up with your own solution.
AVR MCU Source Code and HEX file
The following archive RLV12 Emulator V2.0 AVR Project
has all source files of the AVR project, the project files and the
which is assembled with the option for this Q-Bus RLV12 Emulator V2.0. If you make
changes to the source and assemble it make sure that the you have selected the
correct interface type, which is
; ; RLV12 Assembler Option ; ; 10 RLV12 Emulator V1.0 original Version PDP-11/Hack and Q-Bus with CSR in CPLD ; ; 11 RLV12 Emulator V1.0 original Version PDP-11/Hack and Q-Bus with CSR in MCU ; ; 12 RLV12 for the modified PDP/11-Hack with DMA data register ; ; 21 RLV12 Emulator V2.0 for the Q-Bus with CSR in MCU ; #define rlv12 21 ; Select Assembler Option
As with the previous version of the RLV12 Emulator you need a copy of my
general library files which must be placed in a directory called
that is at the same hierarchy as the project directory (i.e. both directories
must reside in the same main directory). Here you can download the newest
version of my Standard Inlcude Files
To program the CPLDs, an ATF1504 and an ATF1508, you need a programmer like the ATDH1150USB-K USB ISP Cable and the appropriate software. You can use Atmel ISP form Microchip software to directly download the jedec file to the CPLD via the ISP JTAG interface or to create a SVF file that can be used by many SVF players and appropriate hardware to download the configuration to the CPLD. I personally use the ATDH1150USB-K USB ISP Cable and the Atmel ISP software. The following applies to Atmel ISP software only.
To program the two CPLDs on the RLV12 Emulator V2.0 you need a so called
Chain File. This file is just a list of tasks to perform on each CPLD. JTAG
allows to cascade the devices you need to program and each device gets a
consecutive number. In our case we have the
Chip 1 and the
Chip 2. The
first device is the ATF1504AS and the second device is the ATF1508AS. For each
device you specify the action and the input or output file.
When programming the CPLDs, place the
Chain File and the
Jedec files in a
folder. Then start ATMISP and open the
Chain File. Change the Jtag
Program/Verify and selec the appropriate
Jedec file. The
QBUSRLV12V2-B-V2-0.jed goes into
Chip 1 and the file named
QBUSRLV12V2-A-V2-0.jed goes into
Chip 2. There is no risk when selecting
the wrong file as the programmer will notice that the jedec file does not
match the device type. This is definitively an issue if you have large chains
with equal devices as when you mess things up you will have the wrong design
files loaded into the CPLDs.
The following archive contains a sample chain file, the jedec files and the CPLD design files aka. the source code.
CPLD Design, Jedec and Chain File
As awlays the CPLD design files are WinCUPL projects. WinCUPL is as well available from microchip. For more information see here https://www.microchip.com/design-centers/fpgas-and-plds/splds-cplds/pld-design-resources