Theory of Operation

Introduction

The MSCP Emulator is basically a microcontroller that performs all the logical function with some external logic implemented in programmable logic devices that allows the microcontroller to interact with the Q-Bus.

The firmware of the microcontroller implements all the functions necessary to implement a MSCP port and MSCP server. As data storage the microcontroller uses an SD-Card connected via one of the SPI ports. The emulated MSCP units are mapped either to partitions on the SD-Card or to disk image files stored on a FAT-32 formatted partition.

Q-BUS Interface and Timing

The Q-Bus is an asynchronous bus, consisting of a 16 bit bidirectional multiplexed address/data bus, 6 extended address lines and 5 primary control lines. Refer to the DEC LSI-11 Microcomputer Processor Handbook for detailed information concerning operation of the Q-Bus.

The Q-BUS interface builds a bridge between the legacy Q-Bus and the microcontroller and consists of the following basic building blocks

• Q-Bus signal interface circuit that translates the specific parameters of Q-Bus signals to standard TTL input and output signals.
• A main CPLD that implements the data and address path and interacts with the microcontroller to perform DATI, DATO, INIT and IACK cycles. It also provides the necessary data and address registers used by DMA. From the microcontrollers perspective the Q-Bus interface is seen as a set of 8-bit registers and a set of GPIOs that perform certain functions in the CPLD, as well as a source for interrupts.
• A second CPLD that implements the handles the timing and signalling of DMA cycles. There is also a set of GPIOs connected to the microcontroller to either initiate a DMA, detect the completion of a DMA or to abort a DMA cycle that has run for too long

Q-Bus Signal Interface Circuit

For example in Appendix E - LSI-11 Bus Technical Specifications of the MICRO/PDP-ll Handbook manual the electrical characteristics of the Q-Bus signals are defined as following

Q-Bus Drivers

• Output low voltage when sinking 70mA of current: 0.7V maximum
• Output high leakage current when connected to 3.8V: 25µA even if no power is applied
• Load capacitance not to exceed 10pF
• Propagation delay less than 35ns
• Skew less than 25ns

Q-Bus Receivers

• Input low voltage (maximum): 1.3V
• Input high voltage (maximum): 1.7V
• Maximum input current when connected to 3.8Vdc: 80µA even if no power is applied
• Load capacitance not to exceed 10pF
• Propagation delay less than 35ns
• Skew less than 25ns

Unfortunately Q-Bus interface devices are no longer produced and NOS or used devices will make it only difficult for others to build the MSCP Emulator. Therefore I have designed my own Q-Bus interface using still active parts. I have already used this concept with my RLV12 Emulator V2.0 as well as in parts with my Q-Bus Memory.

For the Q-Bus Drivers I’m using SN74F38 open collector NAND gates. These devices specify a maximum output voltage of 0.5V when sinking 64mA, which is I think close enough. As a maximum output current 128mA is specified without however no output voltage is defined for currents over 64mA. Seeing that many existing Q-Bus cards have been using the 74S38 open collector NAND gates to successfully drive Q-Bus signals I assume that the F-series with far better performance is a sufficiently good choice. The propagation delay of 13ns or less in worst case scenarios makes them also comply with the requirements of delay and skew. No specifications for the output capacitance is given, but we can assuem it is far less than 10pF.

For the Q-Bus Receivers I have decided to use SN74HC4049 devices. These are high-speed CMOS buffers which allow for input voltages up to 16V regardless of the operating voltage and even when not powered. Operating voltage is defined to be between 2V and 6V. As a CMOS buffer the transfer characteristics is pretty much symmetrical and the threshold is approximatively 50% of the operating voltage. The threshold are close enough to the Q-Bus specifications when operated with approximatively 3V to 3.3V. At least at room temperature. The output is driven rail to rail so the output signal is compatible with standard TTL inputs. Propagation delay is typically specified only for 2V, 4.5V and 6V. Extrapolating the values to 3.3V shows that they comply with the requirements of receivers regarding delay and skew. The input capacitance is 3.5pF.

Both devices are still manufactured and available in small outline packages which I’m going to use as the MSCP Emulator is design with all SMD components.

This should allow to order MSCP Emulators fully assembled at your favorite PCB manufacturer.

For bidirectional signals a open collector NAND gate together with a high-speed CMOS buffer is used which will then create a transmit and receive signal of the corresponding Q-Bus signal, which is pretty much the same as it was used on real Q-Bus cards using the e.g. DS8641.

Note that using this design the signals on the Q-Bus card side are actually compatible with either 5V or 3.3V logic. Which makes it suitable for later designs using FGPAs or modern microcontroller.s

DATI and DATO cycles

When the PDP-11 accesses the device registers of an MSCP port it either uses DATI or DATO cycles to the IP or SA register of the MSCP hardware. When the main CPLD detects a DATI or DATO cycle to either of these registers it will latch all the necessary information and interrupts the microcontroller.

The interrupt service routine (ISR) of the microcontroller has now approximatively 8µs to respond to the Q-Bus request. Depending on the Q-Bus cycle and the status of the MSCP server the microcontroller will perform the necessary actions required to process the request. First it will check the interrupt lines and in case of a DATI or DATO cycle will read register 4 to identify the type of the request (DATI or DATO), the selected range (device registers or emulated boot ROM) and the address. Then the ISR will proceed with the appropriate function. For a DATO or DATI cycle it will use registers 0 and 1 to transfer the data form or to the Q-Bus. Once the ISR has finished the request it will acknowledge the end of the operation towards the main CPLD using the ACK signal, which then let the main CPLD finish the Q-Bus cycle and assert BRPLY. Depending on the register and data transferred the microcontroller will continue processing the request.

Depending on the Emulation the microcontroller can also set the interface busy for DATI or DATO cycles. In case of an MSCP port, reading the SA register could cause too many interrupts, when the PDP-11 constantly polls the register for errors. This is typically the case during boot operations but is also the case when the system does not use interrupts to signal the end of a MSCP command. Therefore the microcontroller can clear the controller ready bit (CRDY). This will cause the main CPLD to assert the DATI request to the SA register independently of the microcontroller and return a zero value and will not interrupt the microcontroller. This greatly improves the performance during boot and polled IO operations. Only when the microcontroller needs to report a status change or error via the SA register it will assert CRDY and handle the DATI via the ISR.

Similarly for the RLV12 emulation, when the PDP-11 has requested a command to the controller the microcontroller will clear the CRDY bit until the request has been finished. In this case it will affect all DATI or DATO cycles to any of the device register. This is in fact identical to a real RLV12 controller which will not react to DATO cycles during internal operations and always return zero for DATI cycles until the operation has finished and the RLV12 is ready to accept new commands.

IACK cycles

Similar to DATI and DATO cycles the main CPLD will interrupt the microcontroller if the PDP-11 performs an interrupt acknowledge cycle. The main CPLD will monitor the BIAKI signal and in case the MSCP Emulator card has initiated an interrupt by asserting BIRQ4 will block BIAKO from being asserted and will interrupt the microcontroller. The ISR of the microcontroller will be triggered and the firmware will as always check the interrupt lines. When the microcontroller detects that the source of the interrupt is an IACK cycle it will first de-assert the Q-Bus interrupt request line and use register 0 and 1 to set the interrupt vector. It then informs the main CPLD that the IACK processing has been finished which will cause the main CPLD to assert BRPYL and finish the IACK cycle on the Q-Bus

Bus Init

Bus Init is connected to yet another interrupt input of the microcontroller. In this case the ISR will detect a Bus Init cycle. A Bus Init cycle takes approximatively 69 DCJ11 CPU cycles, which depending on the clock speed of the processor corresponds to approximatively 15 to 18µs. The microcontroller will perform all necessary actions to reset the values and states to initialise the MSCP port and server.

DMA

The DMA is controlled by the second CPLD also known as the DMA CPLD. To perform a singel word DMA the microcontroller must first set the registers in the main CPLD. For a DMA write the microcontroller must set the DMA address registers and the DMA data registers. Then it signals a DMA request to the DMA CPLD by asserting the DMR line. The DMA CPLD will assert BDMR on the Q-Bus and observes BDMGI for a grant request. If the microcontroller has requested a DMA the DMA CPLD blocks BDMGO and asserts BSACK. Then it performs a DATO cycle on the Q-Bus. When the DMA has finished the DMA CPLD asserts the DMG line to signal the microcontroller that the DMA request has been performed. It is the duty of the microcontroller to generate a timeout if the DMA has not been performed in due time. In other words, should the DMA CPLD not assert DMG within 13 to 20µs the microcontroller shall abort the DMA by pulsing the ABO line. The DMA CPLD will then reset the DMA state machine and remove the BDMR signal from the Q-Bus.

In case of a DMA read the microcontroller only needs to set the DMA address register before initiating a DMA. When the DMA has finished the microcontroller can then fetch the word received via the DATI cycle of the DMA.

Note that the microcontroller must signal the direction (DATI or DATO) of the DMA cycle via the LSB of the lower byte of the DMA address. This signal is propagated via one of the interface signals between the main and the DMA CPLD as other signals that control the address and data phase, which are used by the main CPLD to present the address or data or load the data into the DMA data register.

Once the DMA has finished the main CPLD will increment the stored DMA address by two. Therefore subsequent DMAs do not need to setup the DMA address.

Main CPLD Register Interface

The microcontroller exchanges information via an 8-bit databus with the CPLD. This register interface, besides the eight data lines, has three register select lines, a read and a write control line.

Register Read Write 0 Q-Bus Data Low Q-Bus Data Low 1 Q-Bus Data High Q-Bus Data High 2 DMA Data Low DMA Data Low 3 DMA Data High DMA Data High 4 Address Info DMA Address Low and DMA Direction Bit 5 - DMA Address High 7 - DMA Address Extension

Note that register 0, 1, 2 and 3 latch the date with the leading edge of the WR signal and register 4, 5 and 7 latch the data when the WR signal is high. Therefore to write into a register the microcontroller should first make sure that both signals, RD and WR, are de-asserted and set the data port to output. As next the microcontroller needs to set the register select lines according to the register you want to write. Then place the data and then create a pulse on WR, i.e. set and clear the WR signal. NO wait states between set and clear are necessary. The microcontroller then turns the data port to input after it has written all the registers it wants to update.

When reading from a register the microcontroller must insert wait states between asserting the RD signal and reading the data port, as the data may only be present at the input after some clock cycles due to internal synchronisation of general purpose inputs. Typically it has to wait at least two clock cycles after it has set the register select signals and asserted RD before reading the data from the input port.

Interface Signals between the main CPLD and the microcontroller

MSCP is a configuration signal for the CPLD. When asserted it will respond to the address of a primary MSCP port, i.e. access to addresses 172150/2₈. When de-asserted the CPLD will respond to addresses 174400..174417₈. This allows to change the hardware to emulate either a RLV12 or a MSCP controller by just changing the firmware of the microcontroller.

INTQ is the interrupt signal from the CPLD towards the microcontroller when the CPLD detects a DATI or DATO cycle to one of the device register addresses, or in case ROM is emulated as well, to one of the ROM addresses. It is an active low signal. A low creates a level1 interrupt at the microcontroller. This interrupt level can interrupt normal operation and interrupt service routines running at interrupt level 0.

INTI is the interrupt signal from the CPLD towards the microcontroller when the CPLD detects a IACK cycle and the emulator is the highest ranking device that initiated an interrupt. This signal is linked to the same interrupt service routine as the ‘INTQ’ signal.

ACK is a signal from the microcontroller that acknowledges the interrupt from the CPLD. This is to inform the CPLD that the requested data has been read from the Q-Bus or written to the Q-Bus data register and the Q-Bus cycle should be finished. The CPLD will then assert BSYNC and finish the Q-Bus cycle. This signal is used to acknowledge DATI, DATO and IACK cycles. The CPLD requires a short pulse from the microcontroller, ie. the microcontroller must assert and shortly after de-assert ACK, this should be done within less than 1µs

CRDY is the controller ready signal. If asserted means that the CPLD should interrupt the microcontroller for DATI and DATO cycles to all device registers. When RLV12 emulation is active de-asserting CRDY will cause the CPLD to no longer interrupt the microcontroller regardless of the device register accessed and will immediately assert BRPLY on behalf of the microcontroller. In case of a DATI the CPLD will return zero as value. This is how the RLV12 controller effectively works during disk IO. In case of MSCP emulation this affects only DATI cycles to the SA register. This register is often used to poll the MSCP port to check for errors. Especially during bootstrap and bootloader execution without interrupts the SA register is often polled. To speed loading the code during this period the microcontroller may de-assert ‘CRDY’ in order to keep the number of interrupts as low as possible. As long as nothing has to be reported there is no need for the microcontroller to just return a zero value.

IRQ when asserted will assert BIRQ4 on the Q-Bus and let the CPLD know that the microcontroller has initiated an interrupt. This will be used during IACK cycles to decide whether to interrupt the microcontroller or to propagate BIAKI to BIAKO on the Q-Bus.

Interface Signals between the DMA CPLD and the microcontroller

DMR is asserted by the microcontroller to inform the CPLD to perform a DMA cycle. Before a DMA cycle is started the microcontroller will need to setup the DMA address and in case of a DMA write needs to place the data into the DMA data register. Once the DMA has been finished the CPLD will inform the microcontroller by asserting DMG. The microcontroller will then de-assert DMR and the CPLD will finish the DMA cycle and de-assert DM. If DMG is not asserted within due time the microcontroller must assuem a bus timoeout and abort the DMA cycle using ABO. Note that the main CPLD will automatically increment the DMA address by two after every DMA cycle. Therefore to transfer a block of data only the start address of a DMA needs to be written by the microcontroller to the main CPLD.

DMG from the CPLD signals the microcontroller has finished the DMA cycle.

ABO is set by the microcontroller to reset the DMA state machine either during initialisation or after the microcontroller detects a bus time. ABO must be asserted and then immediately de-asserted to reset the DMA state machine. As with ACK a short pulse less than 1µs should be applied.

Interface Signals between the main and the DMA CPLD

DMARD this signal is bit0 of DMA address register 4 of the main CPLD and tells the DMA controller the direction of the DMA transfer. The reason this bit is implemented in the main CPLD and not in the DMA controller is that I wanted to avoid any data interface between the microcontroller and the DMA controller just for one bit.

LD during DMA this signal from the DMA controller tells the main CPLD to load the data form the Q-Bus into the DMA data register so the microcontroller can read the data read via DMA after the DMA has finished.

TDOUT this signal from the DMA controller tells the main CPLD to present the content of the DMA data register to the Q-Bus

TADDR this signal from the DMA controller is active during the address phase of the DMA DATI or DATO cycle and tells the main CPLD to present the DMA address register to the Q-Bus

Interface Signals from the Q-Bus to the microcontroller

RINIT is the receive INIT derived from the Q-Bus signal BINIT using one of the inverters in a CD74HC4049 inverter used as Q-Bus receivers. This signal is connected to both CPLDs and the microcontroller. It is used to reset the internal states of the CPLDs and is used as an interrupt input for the microcontroller. This interrupt is linked to the same interrupt service routine as used for DATI, DATO and IACK cycles and executes at level 1. The pin on the microcontroller is configured to initiate an interrupt on both, the rising and falling, edges.