Alternate Decoder Logic using a GAL
Foreword
Initially the goal of the design of the DCJ11 SBC was to avoid any type of programmable logic devices. This means it should only use standard TTL logic devices. However after building the prototype I thought that I could at least add an option which allows to replace the six TTL logic devices with a single GAL.
Replacing the TTL logic with a GAL16V8
This is actually a perfect example why PAL and GAL have been so popular after their appearance. With TTL logic devices you had to be very creative as glue logic often involves the use of inverted signals and requires a combination of NAND, NOR, AND and OR gates. There are medium scale integrated logic devices, like decoders and encoders, but as they have been designed to be versatile they often decode and encode more states or signals than actually used by the glue logic. U8 and U14 (74HCT139 and 74HCT139) are exmaples how a logic device perfectly implements an equation but either has many unused outputs or has additional function blocks that remain unused. Also discrete logic requires to route a signal to many devices. And to make things worse, cascading logic devices increased the response time of the logic implemented.
All these issues are avoided by using GAL. Inputs are available to all equations and are also available inverted. No extra unused outputs. Propagation delay is independant of the logic equation. The glue logic of the DCJ11 SBC perfectly fits in a small GAL. The only inputs needed by the glue logic are
A0, BUFCTL, SCTL, LAIO0, LAIO1, LAIO2, LAIO3, LBS0, LBS1
and the glue logic only generates the following outputs.
OE, WEL, WEU, GPREAD, CE, IO
Therefore a GAL16V8 is sufficient to implement the glue logic.
The SBC has socket U18 prepared that can be used to install the GAL with the following equations. Note that if you install the GAL you don’t have to install the other six TTL logic devices U4, U7, U8, U10, U13, U14. The GAL completely replaces them. Also when installing the GAL you should use a socket as you cannot programm the GALs in-circuit and later cards that go into the expansion slot will take over the decoding alltogether.
Design File for the GAL16V8
Here you have the source code for the GAL. This design file is intended to be used with WinCUPL. WinCUPL can be downloaded from the Microchip web site and is free.
https://www.microchip.com/en-us/products/fpgas-and-plds/spld-cplds/pld-design-resources
Name DCJ11 SBC Decoder;
Partno GAL;
Date 13/04/2025;
Rev 1.3.0;
Designer cbscpe;
Company Netzwerk & Design GmbH;
Assembly None;
Location None;
Device G16V8;
/*
Decoder GAL for the DCJ11 SBC V1.3
This GAL replaces the six TTL logic ICs normally used
to decode the minimal signals on the SBC. But to make
things simpler a GAL has been fitted to the PCB. You
either install the six TTL logic ICs or the GAL but
never both at the same time as they are connected in
parallel. The TTL logic ICs still exist for those who
want to build the SBC but have no access to a GAL or
GAL programmer.
GALs are no longer produced, only Microchip produces
pin replaceable EEPLDs. There are some major differences
between those EEPLDs and GALs. EEPLDs support only about
hundred erase cycles, where as GALs support thousands.
Second the programming algorithm for the EEPLDs is not
documented and I suppose the programmers that support
the EEPLDs are using reverse engineered algorithms.
To compile this PLD design file I use a batch file that
invokes the command line tools that come with WinCUPL.
.\cupl.bat Z:\DCJ11SBC\DCJ11SBC.PLD
To program the GAL I use a T48 programmer from XGecu
and the open source program minipro which runs on Linux
and macOS.
minipro -p GAL16V8D -w DCJ11SBC.jed
*/
PIN 1 = LAIO3;
PIN 2 = LAIO2;
PIN 3 = LAIO1;
PIN 4 = LAIO0;
PIN 5 = LBS0;
PIN 6 = LBS1;
PIN 7 = !SCTL;
PIN 8 = !BUFCTL;
PIN 9 = A0;
PIN 12 = !OE;
PIN 15 = !WEL;
PIN 16 = !WEU;
PIN 17 = !CE;
PIN 18 = !IO;
PIN 19 = !GPREAD;
OE = LAIO3 & LAIO2 & !LAIO1 & !LAIO0 & BUFCTL
# LAIO3 & !LAIO2 & BUFCTL;
CE = !LBS1 & !LBS0;
IO = LBS1 & !LBS0;
WEL = !LAIO3 & !LAIO2 & !LAIO1 & !BUFCTL & SCTL
# !LAIO3 & !LAIO2 & LAIO1 & !A0 & !BUFCTL & SCTL;
WEU = !LAIO3 & !LAIO2 & !LAIO1 & !BUFCTL & SCTL
# !LAIO3 & !LAIO2 & LAIO1 & A0 & !BUFCTL & SCTL;
GPREAD = LAIO3 & LAIO2 & LAIO1 & !LAIO0 & BUFCTL;
To program the GAL I use a XGecu T48 universal programmer and the minipro tool available on github
https://gitlab.com/DavidGriffith/minipro/
peter@MacBook-Air-von-Peter DCJ11SBC % minipro -p GAL16V8D -w DCJ11SBC.jed
Found T48 01.1.32 (0x120)
Warning: T48 support is experimental!
Warning: Firmware is newer than expected.
Expected 01.1.31 (0x11f)
Found 01.1.32 (0x120)
Device code: 4CA19008
Serial code: MH1N82RUHS50LESSGTD27227
VPP=16V
Declared fuse checksum: 0x2C03 Calculated: 0x2C03 ... OK
Declared file checksum: 0xBBD1 Calculated: 0xBBD1 ... OK
JED file parsed OK
Erasing... 0.82Sec OK
Writing jedec file... 3.37Sec OK
Reading device... 0.08Sec OK
Verification OK
peter@MacBook-Air-von-Peter DCJ11SBC %
I have packed all the files related to the GAL design in the following ZIP file DCJ11SBC where you also find the JED-file to program the GAL and the .doc file produced by WinCUPL which gives an overview of the equations, product term usage and the pin layout in a nice format.
Update for GAL with PCB Version 1.3.2
The following extensions to the GAL equations only make sense if you also have installed the optional circuit which supports larger RAMs and/or detects non-existing memory.
Revision 1.3.2 of the project makes some more signals available to the GAL. The following signals have been added in Version 1.3.2
- NXM
- CONT
- MISS
First the logic for the chip enable signal of the memory includes the NXM input. Therefore the memory is no longer mirrored.
MISS is now de-asserted when accessing the memory and hence memory read cycles are now as fast as a read cycle of a DCJ11 can be, it only takes 4 clock cycles. However it requires that the memory installed is fast enough. Memory with access time of 70ns or less is sufficiently fast for clocks up to 20MHz.
CONT is now asserted depending on the access type. It is immediately asserted when writing to existing memory making memory write cycles as short as 8 clock cycles. This is the fastest possible memory write cycle for the DCJ11. It is also asserted immediately when the DCJ11 accesses system registers or internal registers, e.g. the process status at address 1777768 or the MMU registers. When external registers are accessed CONT is now only asserted when SCTL is asserted. This adds two more cycles to the stretched portion of the DCJ11 CPU cycle. Especially as the write pulses are gated with SCTL this increases the write pulses from 1 clock cycle to 3 clock cycle. Therefore even when overclocking the DCJ11 slow samples of the DC319 or CDP6402 will still work.
Name DCJ11 SBC Decoder;
Partno GAL;
Date 13/04/2025;
Rev 1.3.2;
Designer cbscpe;
Company Netzwerk & Design GmbH;
Assembly None;
Location None;
Device G16V8;
/*
Decoder GAL for the DCJ11 SBC V1.3.2
This GAL replaces the six TTL logic ICs normally used
to decode the minimal signals on the SBC. But to make
things simpler a GAL has been fitted to the PCB. You
either install the six TTL logic ICs or the GAL but
never both at the same time as they are connected in
parallel. The TTL logic ICs still exist for those who
want to build the SBC but have no access to a GAL or
GAL programmer.
GALs are no longer produced, only Microchip produces
pin replaceable EEPLDs. There are some major differences
between those EEPLDs and GALs. EEPLDs support only about
hundred erase cycles, where as GALs support thousands.
Second the programming algorithm for the EEPLDs is not
documented and I suppose the programmers that support
the EEPLDs are using reverse engineered algorithms.
To compile this PLD design file I use a batch file that
invokes the command line tools that come with WinCUPL.
.\cupl.bat Z:\DCJ11SBC\DCJ11SBC-V1-3-2.PLD
To program the GAL I use a T48 programmer from XGecu
and the open source program minipro which runs on Linux
and macOS.
minipro -p GAL16V8D -w DCJ11SBC-V1-3-2.jed
*/
PIN 1 = LAIO3;
PIN 2 = LAIO2;
PIN 3 = LAIO1;
PIN 4 = LAIO0;
PIN 5 = LBS0;
PIN 6 = LBS1;
PIN 7 = !SCTL;
PIN 8 = !BUFCTL;
PIN 9 = A0;
PIN 11 = NXM;
PIN 12 = !OE;
PIN 13 = !MISS;
PIN 14 = !CONT;
PIN 15 = !WEL;
PIN 16 = !WEU;
PIN 17 = !CE;
PIN 18 = !IO;
PIN 19 = !GPREAD;
OE = LAIO3 & LAIO2 & !LAIO1 & !LAIO0 & BUFCTL
# LAIO3 & !LAIO2 & BUFCTL;
CE = !LBS1 & !LBS0 & !NXM;
IO = LBS1 & !LBS0;
WEL = !LAIO3 & !LAIO2 & !LAIO1 & !BUFCTL & SCTL
# !LAIO3 & !LAIO2 & LAIO1 & !A0 & !BUFCTL & SCTL;
WEU = !LAIO3 & !LAIO2 & !LAIO1 & !BUFCTL & SCTL
# !LAIO3 & !LAIO2 & LAIO1 & A0 & !BUFCTL & SCTL;
GPREAD = LAIO3 & LAIO2 & LAIO1 & !LAIO0 & BUFCTL;
/*
Assert !MISS only for non-existant RAM, this will shorten the
memory read cycles to 4 clock cycles and make the DCJ11 think
that these are cache hits. You need to install RAM with an
access time of 70ns or less.
*/
MISS = !LBS1 & !LBS0 & NXM;
/*
Modify !CONT to stretch the CPU cycles for writes to external
IO registers so that the write impulse for the DC319 or CDP6402
is increased to match the requiremenets even for clock rates
above 10MHz. By delaying CONT with SCTL for writes to external
IO registers the write pulse will be increased from 1 to 3
clock cycles.
For memory access we also have to assert CONT as read-modify-write
memory cycles use a stretched read cycle.
*/
CONT = !LBS1 & !LBS0 & !NXM
# !LBS1 & !LBS0 & NXM & SCTL
# !LBS1 & LBS0
# LBS1 & !LBS0 & SCTL
# LBS1 & LBS0;
I have also created a ZIP file DCJ11SBC-V1-3-2 with all relevant information to the GAL for the version 1.3.2.
Some remarks regarding GAL
GAL are long obsolete and no longer produced. However in retrocomputing they are quite handy. Because they were no longer produced I thought it was a bad idea to continue to use them. I knew Microchip/Atmel was still producing their ATF family of GAL compatible EEPLDs, but you needed a programmer that supported the proprietary algorithm. There were reverse engineered home-built programmers, but I was not very interested in them and it would require others that reproduce my project would as well have such a home-built programmer. But since I found out that the T48 from XGecu is able to program the ATF SPLDs from Atmel/Microchip and as the ATF16V8 and ATF22V10 are still available even in DIL packages I again started to use GAL or in this case EEPLDs, as the ATF family is named. I still have a large stock of GAL and for simple decoding jobs they are perfect in retrocomputing projects. For more complex tasks however I normally use the ATF150x CPLDs from Atmel/Microchip. Good thing is that all these devices are still available for 5V.
Note that even so the EEPLDs from Microchip are one-to-one replacements for the former Lattice GAL there is one important difference, EEPLDs can only be reprogrammed approx 100 times whereas GALs supported at least 10'000 write cycles.