DCJ11 SBC Memory System

The DCJ11 SBC does not decode all memory addresses. Hence the memory is mirrored every 128kW. Also we only latch addresses A0..A17. The upper four memory addresses A18..A21 are not latched. Even so you can peek and poke into the full range of 4Mbyte of RAM, you actually always see the same 128kW of memory repeated every 128kW. So in other words if you poke a value to address 0 you will see the same value every 128kW and when you overwrite this value using one of the higher addresses it will be visible at address 0 again.

@0/000000 177777
@/177777 
@1000000/177777 
@2000000/177777 
@3000000/177777 0
@0/000000 
@

As you can also see, even so we only have 128kW, all addresses are accepted.

Latching the Additional Address Lines

If you want to add more memory or if you want to detect non-existant memory you have to decode the memory addresses. The first step is to latch the remaining address bits A18..A21. For this you need to install a 74HCT175 at location U6 which is an edge triggered quad D-type Flip-Flop with inverted and non-inverted outputs.

The inverted address for A18 and A19 are already routed to pin 30 and pin 1 of the 32-pin RAM sockets. Pin 1 is not connected on 128kbyte RAM. Pin 30 however is used as the second chip enable of 128kbyte CMOS RAM. As we route the inverted value of A18 to pin 30 this means that the existing 128kW RAM is still selected for the following memory addresses

• 00000000..00777776
• 02000000..02777776
• 04000000..04777776
• 06000000..06777776
• 10000000..10777776
• 12000000..12777776
• 14000000..14777776
• 16000000..16777776

Most importantly the RAM is available at the lowest address. When U6 is installed you still can access the other ranges

• 01000000..01777776
• 03000000..03777776
• 05000000..05777776
• 07000000..07777776
• 11000000..11777776
• 13000000..13777776
• 15000000..15777776
• 17000000..17777776

However nothing happens when you poke a value it will go nowhere

@0/000377 
@1000000/000000 
@2000000/000377 
@1000000/000000 177777
@0/000377 
@2000000/000377 

This is because in these ranges A18 is high and the inverted value is low and as the inverted value connects to CE2 of the 128kbyte RAM ICs, the RAM is not selected and nothing can be written or read.

Note when U6 is not installed pin 30 of the RAM ICs is connected via a pull-up resistor R12 to VCC and permanently enables the chips. U6 overwrites the effect of the pull-up. Per default the pull-up resistor value is 3300Ω. The output of CMOS TTL logic devices is strong enough, they can sink and source up to 4mA and still provide proper logic levels.

Memory Upgrade

When you have installed U6 you can now address more memory. The DCJ11 SBC now supports 512kbyte CMOS memory ICs. Alliance Memory Inc. is still producing 512kbyte CMOS memory in DIP-32 packages. As far as I know they have one model which operates from 2.7V to 5.5V and has a guaranteed access time of 55ns. This will work even for the highest clock rates supported by the DCJ11.

When you now replace the two 128kbyte CMOS RAM with 512kbyte CMOS RAM you now have a DCJ11 SBC with 512kW of memory. Memory is now still mirrored but now the ranges are

• 00000000..03777776
• 04000000..07777776
• 10000000..13777776
• 14000000..17760000

Note that you cannot have memory for the top most 4kW, this range is reserved to the IO-page and includes all internal, external and system registers. Upgrading is optional and the detection of non-existant memory works with 128kW or 512kW installed memory.

NXM - Non Existant Memory

When you have installed the 74HCT175 you can add a 74HCT20 at location U9. The 74HCT20 is a dual quad-input NAND gate. We are using only one NAND gate with the inverted addresses A18..21 as input. Therefore the output of the NAND is high when the DCJ11 addresses memory above the first 128kW, i.e address above 777777₈. This signal, called NXM, is routed to the expansion slot and can be used as non-existant memory indicator. In case you have installed 512kW of memory you need to cut the two jumpers JP5 and JP6 open. This will disable the negated values of A18 and A19 and activate pull-up resistors. In this case the NAND signals only evaluates the inverted values of A20 and A21. NXM is then only asserted when the DCJ11 addresses memory above the first 512kW, i.e. addresses above 3777777₈.

Note you must not cut the jumpers JP5 and JP6 when you only have the initial 128kW of memory installed, else NXM will not be evaluated correctly. The jumpers are solder jumpers and can easily be solder back to the closed position in case you later want to downgrade the memory from 512kW to 128kW.

Installing Optional Logic

The two TTL logic devices are installed beneath the DCJ11. You need to solder them directly to the PCB without sockets. As the DCJ11 uses a socket they perfectly fit under the ceramic chip carrier. Here you can see the SBC with U6 (74HCT175) and U9 (74HCT20) installed

Example of using NXM

By combining NXM with SCTL and CE this can be feed to ABORT via an open collector output. The DCJ11 can now detect non-existant memory and will trap through vector 4 or in case of ODT, it will display the ? which indicates non-existant memory, respectively an aborted CPU cycle.

Here a picture of a preliminary “Hack” of the non-existant memory detection circuit attached to the unfinished DCJ11 SBC, which is still missing the card edge connector.

Here you can see what happens on a DCJ11 SBC with 128kW of memory when you walk through memory adresses using ^J (line-feed) to display repeatedly the next address

@777770/125056 
00777772/127250 
00777774/124252 
00777776/177777 
01000000/?
@

When ABORT is asserted ODT will display a ? instead of the content, which obviously does not exist.

On real PDP-11 systems the non-existant memory signal does not exist, rather the CPU just places the requested address on the bus and if no memory responds to the address an internal time-out will force an abort of the cycle.