DCJ11 Single Board Computer

DCJ11 based Single Board Computer

Initially it all started with some PDP-11/Hack’s on breadboards. Most notably the PDP-11/Hack of Brent Hilpert but as well Len Bayles. And of course my start was using breadboards as well. Later there was my real PDP-11/Hack with all the features needed to run real operating systems. From time to time another attempt to build a PDP-11/Hack pops up. Often the reason behind this is that someone has a DCJ11 laying around.

In Februar 2025 jplr on vcfed presented his idea of building a DCJ11 based trainer that resembled early microcontroller trainers like the KIM-1, AIM-65, Intel SDK-85, etc. with just a small display and a minimal keyboard.

At the same time I was in the process of designing a new CPU board for my PDP-11/Hack, as suggested by another vcfed member, which includes 4Mbyte of on-board memory using the same memory chips as my Q-Bus memory board. However, I was not very reluctant to just modify the existing CPU board by just replacing the memory chips. I always had other ideas for the new CPU board, most notably I wanted it to support power-fail and on-board IO. The first for my own interest as I always asked myself how you implement this and the second to be able to run the CPU board as a stand-alone computer without the need for a bus card and IO boards. But I was struggling with the design as I was not sure how this should to be implemented and I did not want to create numerous versions of a new CPU board.

Thus the idea of building my own version of a minimal single-board computer using the DCJ11. And this was the start of the DCJ11 based Single Board Computer described here.

Introduction

The DCJ11 SBC is a small circuit which contains a minimum of glue logic to play around with a DCJ11. It is based on the idea of the PDP-11/Hack of Brent Hilpert built on breadboards.

The basic SBC only makes use of standard TTL logic and does not require a programmer to program a CPLD or GAL. So it should work out-of-the box.

As a bonus I have added an expansion slot and the SBC is prepared for some optional logic to allow more and fully decoded memory. But more on that later.

Motivation

Even so I have successfully built a variation of Brent Hilperts PDP-11/Hack on a breadboard and later built a fully working PDP-11/Hack with console serial devices and even an emulated harddisk (RLV12 Emulator) there are still some misteries, and I do not fully understand all signals of the DCJ11. And then jplr on vcfed was starting a discussion about a small trainer, this triggered the idea to bring the breadboard to a more stable PCB.

Why would you build a retro 16-bit computer using a DCJ11 and not another 16-bit processor of that era? For me there are several reasons

First I like PDP-11 and it was the first computer I was really working with
Compared to other 16-bit systems it is surprisingly easy and simple
The DCJ11 inlcudes memory management, floating point and exec/user mode
There is plenty of software including powerfull multi-user operating systems

Schematic

The schematic is divided into two sections. At the end of this page you can find a download link for the KiCad project including the schematic and PCB.

Page 1

This page includes the CPU, address and other signal latches, memory, reset logic and the expansion slot

DCJ11 SBC with TTL logic

Page 2

The next page includes the glue logic using TTL logic circuits as well as the place holder for the optional GAL you can install instead of the six TTL logic devices. Also you will find the power-up configuration register and the UART, a DC319. DCJ11 SBC with TTL logic

Components

With the exceptions of resistors and capacitors all components of the basic version are through hole parts. As mentioned all components are standard logic parts except for the DC319 and of course the DCJ11.

Reset Circuit

The reset circuit uses a CMOS hex inverting schmitt trigger 74HCT14 and is very simple. As the DC319 (and the CDP6402) require a positive reset signal (called MR master reset on CDP6402) and the DCJ11 requires a negative reset pulse two inverters are used. I built a proper reset circuit because the DCJ11 behaves very erratic without a proper INIT at power-up. And it is always a good idea to provide a proper reset signal for microcontrollers in general.

To reset the DCJ11 you need to assert INIT for at least 25 clock cycles. The SBC uses a rather high value for the RC values, the reset signal is typically active for 500ms. As mentioned we need a negative pulse as reset for the DCJ11 and a positive pulse as INIT signal for the DC319.

Console UART

I have decided to use a real DC319 as the UART for the console of the SBC because of it’s features and as it fully implements the four registers expected by the ODT of the DCJ11. In addition it will allow us to implement further features using the expansion slots. For those who have no DCJ319 available I will discuss options to use a CDP6402 instead with the help of a small adapter card or expansion board. The minimal requirements for ODT are

Receive Data Flag Bit 7 of RCSR
Receive Data Buffer Low Byte of RBUF
Transmit Buffer Empty Flag Bit 7 of XCSR
Transmit Data Buffer Low Byte of XBUF

Using a real DC319 has the advantage that the baud-rate can be selected by jumpers BRS0..2 and supports all the other features required by a DLV11 normally used as the console of a PDP-11.

With the default setting the DCJ11 will startup into ODT and the user can immediately execute ODT commands as described in chapter 5 of the DCJ11 datasheet.

The DC319 is sometimes seen on ebay. When searching for any offers make sure you also use DC319A, C04090 etc. as search terms, as often sellers have no clue what they are selling. There is a long standing offer on ebay which sells tubes with eleven DC319 for 45$ without shipping. This vendor seems to have a great NOS. (Last checked 31st of March 2025). So in fact the DC319 when order in bulk is cheaper than a CPD6402 per unit and does not require any glue logic. I also created a small adapter board that plugs into the socket for the DC319, using a CDP6402 and some glue logic than emulates the UART features required by ODT.

Memory

The memory is implemented using two byte-wide CMOS SRAM devices. Typically you can use two 128kbyte SRAM ICs like the HM628128, or the AS6C1008. There are two DIP-32 sockets. The memory access logic supports byte writes.

The two DIP-32 sockets are wired with two pull-up resistors for Pins 1 and 30. Pin 1 of the 128kbyte SRAM chips is typically not connected and Pin 30 is used as a second chip enable with positive logic, hence the pull-up resistor which permanently asserts CE2 of the 128kbyte SRAM devices. Note we do not decode the higher address bits and thus the memory is mirrored every 128kW.

Glue Logic

Beside the DCJ11, the DC319 and the memory we need of course some “Glue Logic”. Surprisingly enough the glue logic for a minimal DCJ11 system is very simple.

First you need to know, that the following inputs of the DCJ11 can be either tied to VCC or GND for a default behaviour of the CPU.

The inputs TEST1, PWRF, FPE, EVENT, PARITY, DMR, TEST2 and DV can be tied to VCC. The inputs HALT, IRQ0, IRQ1, IRQ2, IRQ3, MISS and CONT can be tied to GND.

ABORT must not be tied to VCC or GND, this is a bidirectional open collector signal with internal pull-up and if connected then it should be connected via a resistor to VCC.

On the PCB the signals are tied to the respective level using resistors and the signals are brought to the expansion slot and can easily be driven and override the pull-up or pull-down resistors. Therefore the resistors have a rather high value for pull-ups and pull-down to allow standard TTL outputs to drive them with the resistors still in place.

The glue logic consists of three building blocks

Latches for multiplexed signals
Power-Up Configuration
Decoder for memory and console access

DAL, AIO and BS

The following signals are multiplexed and you can use the output ALE to latch the initial value. DAL0..21 are the multiplexed data and address lines. AIO0..3 are the Address Input/Output indicators and BS0..1 are the bank select signals. MAP is a multiplexed output signal that initially shows bit 5 of the memory management register #3. You almost never need this value, unless you need to support a UniBUS and the Unibus Mapping. The second value reflects the DMA request.

As theses signals must be latched using ALE and the active edge of ALE is a falling edge (ALE uses negative logic) we need to invert ALE and produce a LE signal that can be used by the most common TTL latches. For this another inverter of the 74HCT14 of the reset circuit is used to create LE. The circuit latches DAL0..17, AIO0..3 and BS0..1. The SBC uses 74HCT574 edge triggered D-Type Flip-Flops.

Address Input/Output

In the first part of the CPU cycles AIO0..3 define the type of the Bus Cycle. The SBC properly decodes the required AIO codes to generate output enable for the power up configuration register, output enable for the memory and the DCJ319 and individual write enable signals for the lower and the upper byte of a 16-bit word.

AIO Code				Description
1	1	1	1	NIO — Non‐IO or internal CPU cycle, the CPU does not access the bus
1	1	1	0	GP READ — General Purpose Read
1	1	0	1	IACK — Interrupt Acknowledge Cycle
1	1	0	0	Instruction read
1	0	1	1	READ-MODIFY-WRITE no bus lock
1	0	1	0	READ-MODIFY-WRITE bus lock
1	0	0	1	Data Read
1	0	0	0	Demand Read
0	1	0	1	GP WRITE — General Purpose Write
0	0	1	1	Write Byte
0	0	0	1	Write Word

Bank Select

The total address space of a DCJ-11 is split into different banks. Note that this does not extend the address space. You still have only 22 bit addresses. During the first part of the CPU cycle they indicate what type of memory location is accessed.

Bank Select		Description
1	1	Internal register
1	0	External I/O device register
0	1	System register
0	0	Memory

Power-Up Configuration

A 74HCT541 buffer is used to provide a proper power-up configuration for the DCJ11. The DCJ11 needs to be set properly as some power-up configurations will hang-up the DCJ11 if the selected configuration is not installed. The DCJ11 uses a GPREAD cycle to read the power-up configuration. You need to provide proper info on DAL0, DAL1, DAL2, DAL3 and DAL8. A sample circuit is shown in chapter 8.3.4 of the DCJ11 manual. Typically you need to decode the GPREAD address, but in fact this is not necessary for a minimal system. The different GPREAD addresses can be seen in Table 3-2 in chapter 3.7. The power-up configuration is explained in chapter 8.3.3. The SBC has two solder jumpers, JP1 and JP2, in order to set the power-up mode. To start into ODT you need to solder JP1 to connect the input of the 74HCT541 to VCC and JP2 to connect the input of the 74HCT541 to GND. Later we will use the option to power-up with the boot ROM at 173000. Below is a complete overview of the power-up configuration taken from a CPLD design file used in the expansion board described in another post.

/*
	Decode important GPREAD codes
	000		Read Power-Up mode
	002		Read Power-Up mode

	Without FPA, GPREAD is only used to read the power up mode word. This word
	is used to define the startup mode of the DCJ11. This is very important
	else you will have a hard time for a reliable reset to enter a specific
	state.
	
	+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	|15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
	+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
	\___________________________/ | \_______________/ | \_______/ |
	              |               |           |       |     |     |
	              |	              |           |       |     |     |
	Boot address -+	              |           |       |     |     |
	FPA Present ------------------+           |       |     |     |
	Unused -----------------------------------+       |     |     |
	Halt option (0=ODT, 1=Trap 4)---------------------+     |     |
	Power Up mode ------------------------------------------+     |
	Power OK -----------------------------------------------------+
	
	Bits	Power Up Mode
	2	1	
	0	0	Trap Through Location 24
	0	1	ODT
	1	0	Power Up at 17773000 (ROM in IO Page)
	1	1	Power Up at Boot Address with Bits 15..9 forming the
			upper 7 bits of the address and Bits 8..0 set to zero

 */

Note that the power ok is also read during other microroutines, like when starting a program within ODT using the g command. In this case it is important that power ok is asserted, else the program will never start.

The core glue logic

There are several options for the decoding logic and therefore the TTL logic devices should be installed using sockets. The decoding logic only provides the bare minimum required for a PDP-11/Hack and will have to be removed when extending the feature using the expansion board. The SBC itself has two options for the decoding logic which are mutually exclusive. The first uses only standard TTL logic ICs the second uses a programmed GAL16V8 that replaces the six TTL logic devices. It is recommended to use sockets for either option.

To decode the CPU cycles a total of six TTL logic devices is used and located left to the edge card holder for the expansion boards on the PCB. The decoder creates the following signals

CE: Memory Chip Enable uses just BS0 and BS1 as is the case in most DCJ11 based system, the memory is mirrored every 128kW, as we do not decode address lines 18..21. The base version of the SBC also does not make use of a non-existant memory signal as do real PDP-11. this behaviour however can be changed using the expansion slot.
OE: Output Enable uses AIO codes 'b'1100 and 'b'10xx and is used by both, the memory and the UART
WEL: Write Enable Lower byte is asserted when a word or the lower byte is written using AIO codes 'b'00xx and A0. WEL is also used to write to the UART, this is sufficient as there are no writable bits in the upper byte neither in the DC319 nor the CDP6402 circuit.
WEU: Write Enable Upper byte is asserted when a word or the upper byte is written using AIO codes 'b'00xx and A0
IO: External IO uses BS0 and BS1 Hence all access to Bank 'b'10 select the UART. Bank 'b'10 is typically what is known as IO-Page in a PDP-11 system, the DCJ11 uses this bank select code whenever the CPU accesses addresses in the IO-Page, except for internal and system registers, which use a different bank. Note that in ODT you need to specify the full 22-bit address when you want to access external registers, however when the memory management is not enabled a program accesses the IO-Page when it uses addresses above 160000₍₈₎.
GPREAD: this signal is asserted when the DCJ11 emits a GPREAD AIO code and is mostly used to read the power-up configuration. This is required to assure a reliable start into ODT, GPREAD is used for one of the output enable inputs of the 74HCT541 which is wired to provide the proper startup value for bits 0, 1, 2, 3 and 8.
LE: As already mentioned, latch Enable is the inverted !ALE from the DCJ11, ALE is inverted and most transparent or edge triggered latches use a positive logic for the clock, especially the 74x574 but also other compatible devices. LE is created using one of the inverters of the reset logic and is permanent to the SBC.

Power Consumption

The SBC when using HCT CMOS devices for the TTL logic consumes less than 140mA. There is no need for cooling when used without case. The DCJ11 gets about 30°C when running at 18MHz. If it gets hotter something is wrong.

Version History

Prototype Version

There has been a prototype. Although it worked as a PDP-11/Hack I decided not to make the project public. The selection of signals on the expansion slot had some important signals missing and the layout of power was not optimal. It did have the option to latch the upper address bits but there was no decoding of non-existant memory.

Version 1.3

This is the version shown in this article. It has the final expansion slot layout includes an option of latching of the upper address bits and has a proper decoding of non existant memory. However the TEST pin of the DC319 is not connected and needs to be added with a wire.

Version 1.3.1

This version is just version 1.3 with the TEST pin of the DC319 connected to the INIT master reset of the DC319 and now the DC319 initialises properly. Here is a link to the ZIP file of the KiCad Project Version 1.3.1.

Version 1.3.2

This version connects additional signals to the GAL16V8 to allow for variable CPU cycle length. No other changes are made and the basic functionality is still the same.

NXM
CONT
MISS

You can continue to use the TTL logic or you can install a GAL which uses the new signals. RAM reads will be treated as cache hits and will take only 4 clock cycles and IO writes will be extended to 10 clock cycles to make sure the write pulse to the UART are long enough to meet the worst case figures of the DC319 or the CDP6402 when using the small adapter. All other CPU cycles will stay at 8 clock cycles. Note that this version is intended to optimize the CPU cycle length for those who just want a DCJ11 SBC but do not plan to use expansion slot that will source their own logic for CONT and MISS. This if course requires that you have to program a GAL. You can still use the six TTL logic devices, but then you don’t have variable CPU cycle lengths.

I have modified my first V1-3 board to include all changes made in revisions 1 and 2, so the following is the rear view of my sample which inlcudes all features of the Version 1-3-2 board.